Global semiconductor foundries have confirmed initial high-yield runs of 2-nanometer (2nm) silicon wafers, completing the critical technological shift from FinFET architectures to Gate-All-Around (GAA) nanosheet structures.
Breaking Past FinFET Scaling Barriers
As transistor gate channels shrank below 3nm, parasitic capacitance and quantum tunneling leakage significantly impaired performance gains. By surrounding the conducting channel entirely with gate material on all four facets, GAA nanosheet transistors provide far superior electrostatic control and drive current efficiency.
Early device benchmarks suggest up to a 15% increase in compute frequency at matched power profiles, or an equivalent 30% reduction in power draw for consumer mobile and automotive computing modules.